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HT16220 RAM Mapping 328 LCD Controller for I/O MCU
PATENTED
PAT No. : 099352
Technical Document
* Application Note
Features
* Operating voltage: 2.7V~5.2V * External Crystal 32.768kHz oscillator * 1/4 bias, 1/8 duty, frame frequency is 64Hz * Max. 328 patterns, 8 commons, 32 segments * Built-in internal resistor type bias generator * 3-wire serial interface * 8 kinds of time base or WDT selection * Time base or WDT overflow output * Built-in LCD display RAM * R/W address auto increment * Two selectable buzzer frequencies (2kHz or 4kHz) * Power down command reduces power consumption * Software configuration feature * Data mode and Command mode instructions * Three data accessing modes * VLCD pin to adjust LCD operating voltage * HT16220: 64pin LQFP package
HT16220G: Gold bumped chip
General Description
HT16220 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 256 patterns (328). It also supports serial interface, buzzer sound, watchdog timer or time base timer functions. The HT16220 is a memory mapping and multi-function LCD controller. The software configuration feature of the HT16220 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT16220. The HT162X series have many kinds of products that match various applications.
Selection Table
HT162X COM SEG Built-in Osc. Crystal Osc. HT1620 4 32 3/4 O HT1621 4 32 O O HT1622 8 32 O 3/4 HT16220 8 32 3/4 O HT1623 8 48 O O HT1625 8 64 O O HT1626 16 48 O O
Rev. 1.90
1
October 12, 2009
PATENTED
Block Diagram
HT16220
OSCO OSCI CS RD WR DATA VDD VSS BZ BZ T o n e F re q u e n c y G e n e ra to r C o n tro l and T im in g C ir c u it
D is p la y R A M
COM0 L C D D r iv e r / B ia s C ir c u it COM7 SEG0 SEG 31 VLCD W a tc h d o g T im e r and T im e B a s e G e n e r a to r IR Q
Pin Assignment
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG N C C C C 20 21 22 23 24 25 26 27 N N N 31 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9 H T16220 6 4 L Q F P -A 64636261605958575655545352515049 30 29 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
CS NC RD WR DATA VSS VDD VLCD IR Q BZ BZ NC OSCO OSCI T1 T2
171819 20212223242526272829303132 T3 NC
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG NC NC SEG 9 8 7 6
19 18 17 16 15 14 13 12 11 10
SEG SEG SEG SEG SEG SEG COM COM COM COM COM COM COM COM 0 1 2 3 4 5 0 1 2 3 4 5 6 7
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PATENTED
Pad Assignment
SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 23 SEG 22 SEG 20 SEG 21 SEG 24
HT16220
CS
1
55 2
54
53
52
51
50
49
48
47
46
45
44 43 42 41 40
SEG 19 SEG 18 SEG 17 SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG9 SEG8 SEG7
RD WR
3 4
DATA VSS
39 38 37 5 6 7 8 9 36 35 34
VDD VLCD IR Q BZ BZ OSCO OSCI T1 T2 T3
(0 ,0 )
33 32 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SEG0
Min. Bump spacing: 23.102mm Bump size: 76 76mm2 * The IC substrate should be connected to VDD in the PCB layout artwork.
COM0
Bump height: 18mm 3mm
COM1
Chip size: 95 99 (mil)2
COM2
COM3
COM4
COM6
COM7
SEG2 SEG1
SEG3
SEG4
SEG5
SEG6
COM5
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PATENTED
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 X -1068.102 -1068.102 -1068.102 -1068.102 -1046.545 -1068.102 -1068.102 -1068.102 -1068.102 -1068.102 -1068.102 -1068.102 -1068.102 -1068.102 -1068.102 -546.419 -447.320 -255.590 -156.490 35.241 134.340 279.715 378.815 477.835 576.935 675.954 775.056 874.074 Y 1142.255 941.875 842.776 614.987 379.670 274.635 175.574 -1.490 -213.816 -403.664 -608.980 -708.000 -858.985 -958.005 -1124.635 -1144.760 -1144.760 -1144.760 -1144.760 -1144.760 -1144.760 -1144.760 -1144.760 -1144.760 -1144.760 -1144.760 -1144.760 -1144.760 Pad No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 X 973.176 1072.194 1094.145 1094.145 1094.145 1094.145 1094.145 1094.145 1094.145 1094.145 1094.145 1094.145 1094.145 1094.145 1094.145 233.365 134.264 35.245 -63.855 -162.874 -261.975 -360.995 -460.096 -559.115 -658.216 -757.234 -856.334
HT16220
Unit: mm Y -1144.760 -1144.760 -130.495 -31.395 67.624 166.725 265.745 364.846 463.865 562.966 661.984 761.086 860.104 959.206 1058.224 1142.380 1142.380 1142.380 1142.380 1142.380 1142.380 1142.380 1142.380 1142.380 1142.380 1142.380 1142.380
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PATENTED
Pad Description
Pad No. Pad Name I/O Description
HT16220
1
CS
I
Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or written to the HT16220 are disabled. The serial interface circuit is also reset But if the CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT16220 are all enabled. READ clock input with pull-high resistor. Data in the RAM of the HT16220 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch the clocked out data. WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT16220 on the rising edge of the WR signal. Serial data input or output with pull-high resistor Negative power supply, ground Positive power supply LCD operating voltage input pad. Time base or watchdog timer overflow flag, NMOS open drain output. 2kHz or 4kHz tone frequency output pair Crystal oscillator output pin Crystal oscillator input pin Not connected LCD common outputs LCD segment outputs
2
RD
I
3 4 5 6 7 8 9, 10 11 12 13~15 16~23 24~55
WR DATA VSS VDD VLCD IRQ BZ, BZ OSCO OSCI T1~T3 COM0~COM7 SEG0~SEG31
I I/O 3/4 3/4 I O O O I I O O
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 5.5V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 Parameter Operating Voltage Operating Current 5V IDD2 3V Operating Current 5V ISTB 3V Standby Current 5V VIL 3V Input Low Voltage 5V DATA, WR, CS, RD 0 No load, Power down mode Test Conditions VDD 3/4 3V Conditions 3/4 No load or LCD ON Crystal oscillator No load or LCD OFF Crystal oscillator Min. 2.7 3/4 3/4 3/4 3/4 3/4 3/4 0 Typ. 3/4 3/4 3/4 3/4 3/4 1 2 3/4 3/4 Max. 5.2 50 65 20 30 8 16 0.6 1.0
Ta=25C Unit V mA mA mA mA mA mA V V
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PATENTED
Symbol Parameter Test Conditions VDD 3V Input High Voltage 5V IOL1 3V BZ, BZ, IRQ 5V IOH1 3V BZ, BZ 5V IOL1 3V DATA 5V IOH1 3V DATA 5V IOL2 3V LCD Common Sink Current 5V IOH2 3V LCD Common Source Current 5V IOL3 3V LCD Segment Sink Current 5V IOH3 3V LCD Segment Source Current 5V RPH 3V Pull-high Resistor 5V DATA, WR, CS, RD 50 100 VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DATA, WR, CS, RD 4.0 0.9 1.7 -0.9 -1.7 200 250 -200 -250 15 100 -15 -45 15 70 -6 -20 100 Conditions Min. 2.4 Typ. 3/4 3/4 1.8 3.0 -1.8 -3.0 450 500 -450 -500 40 200 -30 -90 30 150 -13 -40 200
HT16220
Max. 3.0 5.0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 300 150 Unit V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA kW kW
VIH
A.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3/4 3/4 3V Serial Data Clock (WR Pin) 5V fCLK2 3V Serial Data Clock (RD Pin) 5V tCS Serial Interface Reset Pulse Width (Figure 3) 3/4 3V tCLK WR, RD Input Pulse Width (Figure 1) 5V Read mode 3.34 Read mode Write mode 6.67 1.67 CS Write mode Duty cycle 50% Duty cycle 50% Conditions Crystal oscillator External clock source Crystal oscillator n: Number of COM Min. 3/4 3/4 3/4 3/4 4 4 3/4 3/4 500 3.34 Typ. 32768 32768 64 n/fLCD 3/4 3/4 3/4 3/4 600 3/4 3/4 3/4 3/4 Max. 3/4 3/4 3/4 3/4 150 300 75 150 3/4 125 3/4 125 3/4
Ta=25C Unit Hz Hz Hz sec kHz kHz kHz kHz ns ms
fSYS fLCD tCOM fCLK1
System Clcok LCD Frame Frequency LCD Common Period
ms
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PATENTED
Symbol t r, t f tSU th tSU1 th1 Parameter Rise/Fall Time Serial Data Clock (Figure 1) Setup Time for DATA to WR, RD Serial Data Clock (Figure 2) Hold Time for DATA to WR, RD Serial Data Clock (Figure 2) Setup Time for CS to WR, RD Clock Width (Figure 3) Hold Time for CS to WR, RD Clock Width (Figure 3) Tone Frequency (2kHz) Tone Frequency (4kHz) tOFF tSR Note: VDD OFF Times (Figure 4) VDD Rising Slew Rate (Figure 4) Test Conditions VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 Crystal oscillator Crystal oscillator VDD drop down to 0V 3/4 Min. 3/4 60 500 500 50 3/4 3/4 20 0.05 Typ.
HT16220
Max. Unit
120 120 600 600 100 2 4 3/4 3/4
160 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
ns ns ns ns ns kHz kHz ms V/ms
ftone
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal Power-on Reset (POR) circuit will not operate normally. 2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for 20ms (min.) before rising to the normal operating voltage.
V A L ID D A T A
tf W R,RD C lo c k 90% 50% 10%
tr
-V tC
LK
DD
DB
V th
DD
50% ts
u
GND V
DD
tC
LK
GND
W R,RD C lo c k
50%
-G N D
Figure 1
Figure 2
tC
S
CS
50% tS
U1
-V
DD
th
1
GND -V
DD
VDD
W R,RD C lo c k
0V
tS
R
50% F IR S T C lo c k
tO
FF
LAST C lo c k
GND
Figure 3
Figure 4. Power-on Reset Timing
Rev. 1.90
7
October 12, 2009
PATENTED
Functional Description
Display Memory - RAM Structure The static display RAM is organized into 644 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can beaccessed by theREAD,WRITEand READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. Time Base and Watchdog Timer - WDT The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will stay at a logic low level until the CLR WDT or the IRQ DIS command is issued.
COM7 SEG0 SEG1 SEG2 SEG3 7 5 6 3 4 COM6 COM5 COM4 1 2 COM3
HT16220
If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. Buzzer Tone Output A simple tone generator is implemented in the HT16220. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. Command Format The HT16220 can be configured by the software setting. There are two mode commands to configure the HT16220 resource and to transfer the LCD display data.
COM2 COM1 COM0 0
A d d r e s s 6 B its (A 5 , A 4 , ...., A 0 )
SEG 31 D3 D2 D1 D0
63 Addr D a ta D3 D2 D1 D0
62 Addr D a ta
D a ta 4 B its (D 3 , D 2 , D 1 , D 0 )
RAM Mapping
T im e B a s e C lo c k S o u r c e /2 5 6 V CLR T im e r
DD
T IM E R
E N /D IS
IR Q
W D T E N /D IS D CK R Q IR Q E N /D IS
W DT /4
CLR
W DT
Timer and WDT Configurations
Rev. 1.90
8
October 12, 2009
PATENTED
The following are the data mode ID and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Name TONE OFF TONE 4K TONE 2K Mode Data Data Data Command Command Code 0000-1000-X 010X-XXXX-X 0110-XXXX-X Turn-off tone output Turn-on tone output, tone frequency is 4kHz Turn-on tone output, tone frequency is 2kHz ID 110 101 101 100 Function
HT16220
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will be reset also. The CS pin returns to 0, a new operation mode ID should be issued first.
Timing Diagrams
READ Mode (Command Code : 1 1 0)
CS
WR
RD
DATA
1 1
0
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3 1
1
0
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
READ mode (successive address reading)
CS
WR
RD
DATA
1 1
0
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
Rev. 1.90
9
October 12, 2009
PATENTED
WRITE Mode (Command Code : 1 0 1)
CS
HT16220
WR
DATA
1 0
1
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3 1
0
1
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
WRITE Mode (Successive Address Writing)
CS
WR
DATA
1 0
1
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
READ-MODIFY-WRITE Mode (Command Code : 1 0 1)
CS
WR
RD
DATA
1 0
1
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3 1
0
1
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
READ-MODIFY-WRITE Mode (Successive Address Accessing)
CS
WR
RD
DATA
1 0
1
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 1 )
D a ta (M A + 2 )
Rev. 1.90
10
October 12, 2009
PATENTED
Command Mode (Command Code : 1 0 0)
HT16220
CS
WR
DATA
1 0
0
C8
C7
C6
C5
C4
C3
C2
C1
C0 C o m m a n d ...
C8
C7
C6
C5
C4
C3
C2
C1
C0 Com m and or D a ta M o d e
Com m and 1
Com m and i
Mode (Data And Command Mode)
CS
WR
DATA
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
RD
Rev. 1.90
11
October 12, 2009
PATENTED
Application Circuits
HT16220
CS * RD WR
VDD *V R VLCD
MCU
*R
DATA
H T16220
BZ P ie z o
BZ
IR Q
OSCI CO M 0~CO M 7 SEG 0~SEG 31 OSCO
C r y s ta l 3 2 7 6 8 H z O s c illa to r
1 /4 B ia s , 1 /8 D u ty
LCD
Note:
Panel
The connection of IRQ and RD pin can be selected depending on the requirement of the MCU. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW20%. Adjust R (external pull-high resistance) to fit users time base clock.
Command Summary
Name READ WRITE READ-MODIFYWRITE SYS DIS SYS EN LCD OFF LCD ON TIMER DIS WDT DIS TIMER EN WDT EN TONE OFF CLR TIMER CLR WDT TONE 4K TONE 2K IRQ DIS IRQ EN ID Command Code D/C D D D C C C C C C C C C C C C C C C Function Read data from the RAM Write data to the RAM Read and Write data to the RAM Turn off both system oscillator and LCD Yes bias generator Turn on system oscillator Turn off LCD display Turn on LCD display Disable time base output Disable WDT time-out flag output Enable time base output Enable WDT time-out flag output Turn off tone outputs Clear the contents of the time base generator Clear the contents of the WDT stage Tone frequency output: 4kHz Tone frequency output: 2kHz Disable IRQ output Enable IRQ output Yes Yes Yes Yes Yes Def. 1 1 0 A5A4A3A2A1A0D0D1D2D3 1 0 1 A5A4A3A2A1A0D0D1D2D3 1 0 1 A5A4A3A2A1A0D0D1D2D3 1 0 0 0000-0000-X 1 0 0 0000-0001-X 1 0 0 0000-0010-X 1 0 0 0000-0011-X 1 0 0 0000-0100-X 1 0 0 0000-0101-X 1 0 0 0000-0110-X 1 0 0 0000-0111-X 1 0 0 0000-1000-X 1 0 0 0000-1101-X 1 0 0 0000-1111-X 1 0 0 010X-XXXX-X 1 0 0 0110-XXXX-X 1 0 0 100X-0XXX-X 1 0 0 100X-1XXX-X
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PATENTED
Name F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL Note: X : Dont care A5~A0 : RAM address D3~D0 : RAM data D/C : Data/Command mode Def. : Power on reset default ID Command Code D/C C C C C C C C C C C Function Time base clock output: 1Hz The WDT time-out flag after: 4s Time base clock output: 2Hz The WDT time-out flag after: 2s Time base clock output: 4Hz The WDT time-out flag after: 1s Time base clock output: 8Hz The WDT time-out flag after: 1/2s Time base clock output: 16Hz The WDT time-out flag after: 1/4s Time base clock output: 32Hz The WDT time-out flag after: 1/8s Time base clock output: 64Hz The WDT time-out flag after: 1/16s Time base clock output: 128Hz The WDT time-out flag after: 1/32s Test mode, user dont use. Normal mode
HT16220
Def.
1 0 0 101X-0000-X 1 0 0 101X-0001-X 1 0 0 101X-0010-X 1 0 0 101X-0011-X 1 0 0 101X-0100-X 1 0 0 101X-0101-X 1 0 0 101X-0110-X 1 0 0 101X-0111-X 1 0 0 1110-0000-X 1 0 0 1110-0011-X
Yes
Yes
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base or WDT clock frequency can be derived from a 32.768kHz crystal oscillator or an external 32768Hz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT16220 after power on reset, for power on reset may fail, which in turn leads to malfunctioning of the HT16220.
Rev. 1.90
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PATENTED
Package Information
64-pin LQFP (7mm7mm) Outline Dimensions
C D 48 33 G H
HT16220
I 49 32 F
A B
E
64
17 K 1 16 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 8.9 6.9 8.9 6.9 3/4 0.13 1.35 3/4 0.05 0.45 0.09 0 3/4 3/4 3/4 3/4 3/4 3/4 Nom. 3/4 3/4 3/4 3/4 0.4 Max. 9.1 7.1 9.1 7.1 3/4 0.23 1.45 1.6 0.15 0.75 0.20 7
Rev. 1.90
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PATENTED
HT16220
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.90
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October 12, 2009

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